The present invention relates to a plasma display apparatus (a PDP apparatus) used as a display unit for a personal computer or work station, a flat TV, or a plasma display for displaying advertisements, information, etc.
AC-type color PDP apparatuses include various types and systems such as two- or three-electrode types, an address/display non-separation system in which a period (address period) during which cells to be lit are selected and a display period (sustain period) during which a discharge is caused to occur for light emission to produce a display are shifted sequentially, and an address/display separation system in which the address period and the sustain period are separated from each other. In most systems, a PDP apparatus has at least a configuration in which a plurality of electrodes arranged in parallel to each other intersect another plurality of electrodes, and in this configuration, it is necessary to drive each electrode independently. The present invention can be applied to any PDP apparatus employing any system provided that the PDP apparatus has a configuration in which such a plurality of electrodes are driven independently. Here, a three-electrode type address/display separation system PDP apparatus, which is currently in practical use and is most widely used, is taken as an example in the following explanation. However, the present invention is not limited to this type.
FIG. 1 is a diagram showing a fundamental configuration of a three-electrode type address/display separation system PDP apparatus. On a first substrate making up a plasma display panel 10, sustain (X) electrodes and scan (Y) electrodes are provided by turns in parallel to each other and they are covered with a dielectric layer. On a second substrate facing the first substrate, address electrodes extending in a direction perpendicular to the X and Y electrodes are provided and the surfaces of the electrodes are covered with a dielectric layer. Further, on the second substrate, stripe-shaped partitions extending in parallel to the address electrodes are arranged between the address electrodes, or two-dimensional grid-shaped partitions arranged between the address electrodes and between the pairs of the X and Y electrodes are provided and, after phosphor layers are formed in grooves in the partitions, the first and second substrates are bonded together to each other at a predetermined distance. Discharge spaces are formed between the first and second substrates and a discharge gas, which is a mixture of neon, xenon, etc., is enclosed therein. A display cell is defined at the intersection of a pair of neighboring X and Y electrodes and the address electrode. In a PDP apparatus employing a normal system rather than an ALIS system, which will be described later, a display cell is defined between a pair of X and Y electrodes, and no display cell is defined between neighboring pairs of X and Y electrodes.
As shown in FIG. 1, the PDP apparatus comprises, besides the plasma display panel 10, an address driver 11 for driving the address electrodes, a Y scan driver 12 for driving the Y electrodes, a Y sustain circuit 13 for supplying a Y sustain signal to the Y scan driver 12, an X sustain circuit 14 that drives so as to supply an X sustain signal to the X electrodes, and a control circuit 15 for controlling each part. As shown schematically, the X sustain circuit 14 has only one output and drives the commonly connected X electrodes. In contrast to this, the Y scan driver 12 drives each of the Y electrodes independently and the address driver 11 drives each of the address electrodes independently.
FIG. 2 is a diagram showing drive waveforms in the PDP apparatus shown in FIG. 1. A fundamental drive sequence of an address/display separation system PDP apparatus comprises a reset period during which all of the display cells are put into a uniform state, an address period during which display cells to be lit are selected, and a sustain period during which the selected display cells are made to emit light. In the PDP apparatus, only the selection of a lit state or unlit state of each display cell can be made and the control of the intensity of light emission is not possible. Hence, one display frame is made up of a plurality of subfields having the fundamental drive sequence as shown in FIG. 2, and a lit state or unlit state of each display cell is selected in each subfield, and a gradated display is produced by combining the luminance of each subfield. In order to efficiently produce a gradated display, the ratio of luminance of each subfield, that is, the ratio of the number of sustain pulses to be applied during the sustain period in each subfield, is set that each term differs from another. For example, the ratios are 1:2:4:8.
As shown in FIG. 2, during the reset period, a voltage Va is applied to each of the address electrodes, a voltage Vw is applied to the common X electrodes, and 0 V is applied to each of the Y electrodes. Due to this, a discharge is caused to occur between the X electrode and the Y electrode and between the address electrode and the Y electrode in each of the display cells and all of the display cells are put into a uniform state. During the following address period, in a state in which a voltage Vx is applied to the common X electrodes and a voltage −Vyl is applied to each of the Y electrodes, a scan pulse having a voltage −Vy is applied sequentially to the Y electrodes and an address pulse having the voltage va is applied to the address electrode in a display cell to be lit in synchronization with the application of a scan pulse. An address discharge is caused to occur between the Y electrode to which a scan pulse has been applied and the address electrode to which an address pulse has been applied, and wall charges are accumulated on the surface of the dielectric layer on the electrode in the display cell to be lit. By applying an address pulse while sequentially applying a scan pulse to each of the Y electrodes, the display cells to be lit are selected in the entire surface. During the sustain period, in a state in which the voltage Va is applied to the address electrode, a sustain pulse having a voltage Vs is applied alternately to the Y electrode and the X electrode. In the display cell in which wall charges have been formed during the address period, a sustain discharge is caused to occur because the voltage due to the wall charges is added to the voltage Vs of a sustain pulse and the discharge start voltage is exceeded, but in the cell in which wall charges have not been formed during the address period, a sustain discharge is not caused to occur because there is no voltage due to wall charges and the voltage Vs of a sustain pulse alone is not sufficient to exceed the discharge start voltage. In the display cell in which a sustain discharge has been caused to occur, wall charges having the opposite polarity are formed by the sustain discharge, therefore, if a sustain pulse is applied to the X electrode, a sustain discharge is caused to occur. If, in this manner, a sustain pulse is applied repeatedly, a sustain discharge is caused to occur repeatedly in the selected display cell.
The configuration and drive waveforms of the PDP apparatus explained in FIG. 1 and FIG. 2 are only examples, and other various configurations and drive methods have been proposed. Although no detailed explanation will be given here, the present invention can be applied to any PDP apparatus.
FIG. 3 is a diagram showing an example of a configuration of each drive circuit in the PDP apparatus explained in FIG. 1 and FIG. 2. The address driver 11 has driver circuits 16 consisting of two transistors AT1 and AT2 connected in series between a power source of the voltage Va and a GND power source, the number of the driver circuits 16 being equal to that of the address electrodes. The connection node of the transistors AT1 and AT2 is connected to each address electrode. When the transistor AT1 is turned on, the voltage Va is applied to the address electrode and when the transistor AT2 is turned on, 0 V is applied to the address electrode.
The Y scan driver 12 has driver circuits 17 consisting of two transistors ST1 and ST2 connected in series between a power source of the voltage −Vy1 and a power source of the voltage −Vy, and two diodes D1 and D2 connected to the connection node of the two transistors ST1 and ST2, the number of the driver circuits 17 being equal to that of the Y electrodes. The diode D1 is connected to a GND power source via a transistor in the Y sustain circuit 13 and the diode D2 is connected to a power source of the voltage Vs via a transistor in the Y sustain circuit 13. During the address period, both the transistors in the Y sustain circuit 13 are turned off and the voltage −Vy1 is output by turning the transistor ST1 on, and when a scan pulse is applied, the ST1 is turned off and at the same time the ST2 is turned on. During the sustain period, both the ST1 and ST2 are turned off and the two transistors in the Y sustain circuit 13 are turned on and off by turns. Due to this, the voltages Vs and GND are applied by turns from the Y sustain circuit 13 via the diodes D1 and D2.
The X sustain circuit 14 has four transistors serving as switches for making connections to the voltages Vw, Vx, Vs and 0 V (GND), respectively, and the respective voltages can be applied to the X electrode by turning on the respective transistors.
As a sustain discharge is caused to occur between the X electrode and the Y electrode, the X electrode and the Y electrode are called the sustain electrode. As a scan pulse is applied to the Y electrode, the Y electrode is called the scan electrode. The Y electrode is called the scan electrode and the X electrode is called the sustain electrode here.
As described above, the Y scan driver 12 has the driver circuits 17 consisting of the two transistors ST1 and ST2 and the two diodes D1 and D2, the number of the driver circuits 17 being equal to that of the scan (Y) electrodes, and a scan pulse is output sequentially from each driver circuit 17. Because of this, the Y scan driver 12 further comprises a shift register, which shifts a signal indicating the output position of a scan pulse sequentially, and the output of the shift register is inputted to the plurality of the scan driver circuits 17. The address driver 11 has the driver circuits 16 consisting of the transistors AT1 and AT2, the number of the driver circuits 16 being equal to that of the address electrodes and an address pulse is output from each driver circuit 16. Because of this, the address driver 11 further comprises a shift register, which shifts address data sequentially, and the output of the shift register is inputted to the plurality of the driver circuits 16 when the shift operation corresponding to the length of the address data is completed.
As described above, a shift register for setting data to be output is, in general, necessary for a driver that outputs a plurality of drive signals independently. In general, therefore, the Y scan driver 12 and the address driver 11 are realized by using driver ICs, into which a shift register, a latch circuit for latching the output of the shift register and a plurality of driver circuits for outputting a drive signal corresponding to the output of the latch circuit have been integrated. By the way, it is not necessary to provide a diode to a driver IC to be used in the address driver 11 but a driver IC to be used in the Y scan driver 12 is provided with diodes.
The number of driver circuits provided in a driver IC is 16 or 64, and currently, a driver IC having 64 driver circuits is widely used and, corresponding to this, a 64-bit shift register or latch circuit is provided. For example, if the plasma display panel shown in FIG. 1 has a configuration in which 1,024×768 display cells are arranged, the scan driver 12 is made up of twelve 64-bit driver ICs in a cascade connection. The address driver 11 is made up of sixteen 64-bit driver ICs and each bit of 16-bit display data is supplied to each IC, and the sixteen 64-bit driver ICs are operated in parallel.
FIG. 4 is a diagram showing a configuration of a driver IC 21. A 64-bit driver IC is considered here. As shown schematically, the IC 21 comprises a 64-bit shift register 22 for shifting input data Din sequentially in accordance with a clock CLK, a 64-bit latch 23 for latching the output of the 64-bit shift register in accordance with a latch enable signal LE, 64 output drivers 24-1 to 24-64 for outputting a drive signal in accordance with each of the 64 outputs of the 64-bit latch 23, and diodes D1-1 to D1-64 and D2-1 to D2-64 connected between each output of the 64 output drivers 24-1 to 24-64 and a power source terminal VL and between that and a power source terminal VH, respectively. The 64 output drivers 24-1 to 24-64 select and output each output of the 64 outputs of the 64-bit latch 23 or the output is put into a high-impedance (Hi-Z) state in accordance with an output control signal OC. To be specific, when used as the Y scan driver, the outputs of the output drivers 24-1 to 24-64 become Hi-Z during the sustain period, and during the address period, the output drivers 24-1 to 24-64 output in accordance with each of the 64 outputs of the 64-bit latch 23. During the sustain period, the GND and the sustain voltage Vs are supplied alternately to power terminals VH1 to VH64 and VL1 to VL64 and a sustain pulse is applied to the respective scan electrodes through the respective diodes D1-1 to D1-64 and D2-1 to D2-64. Due to this, the diodes D1-1 to D1-64 and D2-1 to D2-64 produce heat but the amount of heat produced relates to the drive capacity and discharge current of the scan electrode and a problem is brought about: if the drive capacity and discharge current of the scan electrode are large, the amount of heat produced will become accordingly large.
It is desirable that the specifications of a driver IC, such as drive performance and the number of bits, are specified in accordance with the specifications of a PDP apparatus as a product, but there arise problems: if the number of the PDP apparatus to be-manufactured is not so large, the number of the driver ICs having the proper specifications is not sufficiently large, resulting in a high cost; and a long period of time is required for commercially introducing a new driver IC. Therefore, if a dedicated IC is designed and made commercially available after the specifications of a PDP apparatus are determined, the shipment of the PDP apparatus is delayed and sales chances will be missed. Hence, there may be a case where a driver circuit for a PDP apparatus is realized by using already manufactured driver ICs that have already been made commercially available.
The configuration and drive waveforms of the PDP apparatus explained in FIG. 1 and FIG. 2 are only one example, and other various configurations and drive methods have been proposed. In Japanese Unexamined Patent Publication (Kokai) No. 9-160525, an ALIS system plasma display apparatus (PDP apparatus) has been disclosed, in which the number of display lines can be doubled using the same number of X electrodes and Y electrodes of the conventional PDP apparatus. The details of the configuration of an ALIS system PDP apparatus will be described later. FIG. 5 shows wiring between Y electrodes and driver IC outputs in an ALIS system PDP apparatus, in which a Y scan driver has been realized by using the driver ICs shown in FIG. 4. The plasma display panel (PDP) 10 used here comprises 385 sustain electrodes and 384 scan electrodes, and 768 display lines are defined. The Y scan driver is mounted on a film and connected to the Y electrode terminals of the PDP 10 by thermal compression bonding using an anisotropic conductive film but, because of the conditions on the thermal compression bonding apparatus and the connection performance, the 384 Y electrodes are divided into two blocks each having 192 Y electrodes and are connected to the driver ICs through two groups of output terminals C1 and C2. In an ALIS system PDP apparatus, as it is necessary to drive odd-numbered scan electrodes and even-numbered scan electrodes independently, a Y scan driver is divided into an odd number Y scan driver for driving odd-numbered scan (Y) electrodes and an even number Y scan driver for driving even-numbered scan electrodes. Because of this, it is necessary to divide the 192 scan electrodes in one block into a group of the 96 odd-numbered electrodes and the other group of the 96 even-numbered electrodes and drive the two groups independently.
Therefore, in the case where eight 64-bit driver ICs are used, the output terminals of each IC and scan electrodes Y1 to Y384 are connected as shown in FIG. 5. To be specific, the 64 odd-numbered scan electrodes Y1 to Y127 are connected to the outputs of a first odd number IC 21-01, the 32 odd-numbered scan electrodes Y129 to 191 to the outputs of a second odd number IC 21-02, the 64 odd-numbered scan electrodes Y193 to Y319 to the outputs of a third odd number IC 21-03, and the 32 odd-numbered scan electrodes Y321 to 383 to the outputs of a fourth odd number IC 21-04, and similarly, the 64 even-numbered scan electrodes Y2 to Y128 are connected to the outputs of a first even number IC 21-El, the 32 even-numbered scan electrodes Y130 to Y192 to the outputs of a second even number IC 21-E2, the 64 even-numbered scan electrodes Y194 to Y320 to the outputs of a third even number IC 21-E3, and the 32 even-numbered scan electrodes Y322 to Y384 to the outputs of a fourth even number IC 21-E4. A signal OSD1 is a signal that commands the start of the first half of the address period, a signal ESD1 is a signal that commands the start of the second half of the address period and they are each inputted to the first odd number IC 21-01 and the first even number IC 21-E1 as the data input signal Din, respectively. Similarly, a signal OSD2 and a signal ESD2 are each inputted to the third odd number IC 21-03 and the third even number IC 21-E3 as the data input signal Din, respectively. The clock signal CLK is connected to each IC and the operation of each IC is performed with the clock cycles being synchronized with each other, but the connection of the clock signal CLK is not shown in FIG. 5 and is not shown also in the following figures.
When the signal OSD1 is inputted at the beginning of the first half of the address period, the first odd number IC 21-01 starts the shift operation in accordance with the cycle of the clock signal CLK and outputs a scan pulse sequentially to the 64 odd-numbered scan electrodes Y1 to Y127. Upon outputting a scan pulse to the electrode Y127, the first odd number IC 21-01 outputs a carry C. When the carry C is inputted as the data input signal Din, the second odd number IC 21-02 starts the shift operation and outputs a scan pulse sequentially to the 32 odd-numbered scan electrodes Y129 to Y191 at the clock cycle after that at which a scan pulse is output to the Y127. The second odd number IC 21-02 outputs more 32 scan pulses sequentially after outputting the 32 scan pulses, but these are not applied to the scan electrodes and, therefore, the operation of the PDP apparatus is not affected.
At the timing, after that, at which scan pulses are output to the Y1 to Y191, the signal OSD2 is inputted and the third odd number IC 21-03 starts the shift operation and outputs a scan pulse sequentially to the 64 odd-numbered scan electrodes Y193 to Y319. Then, after receiving the output of the carry C from the previous IC, the fourth odd number IC 21-04 also outputs a scan pulse sequentially to the 32 odd-numbered scan electrodes Y321 to Y383.
When the signal ESD1 is inputted at the beginning of the second half of the address period, the same operation is performed and a scan pulse is output sequentially to the even-numbered scan electrodes.
Conventionally, as described above, when a plurality of driver ICs were used, a cascade connection was employed so that the carry output from the previous driver IC was inputted to the data input Din of the next driver IC. Therefore, when some of the outputs of the driver IC were not used as shown in FIG. 5, wiring was made so that all of the outputs of the first and third odd number and even number driver ICs were used and some of the outputs of the second and fourth odd number and even number driver ICs were not used. In other words, the unused outputs of the driver ICs were distributed unevenly.
As described above, therefore, there may be a case where some outputs of the driver ICs are not used, in other words, some outputs of the driver ICs are excess depending on the number of electrodes, the number of output terminal groups for connecting electrodes and drivers, the number of electrodes per output terminal group, the number of driver IC outputs, whether an ALIS system or a normal system is used, etc.